1. Field of the Invention
The present invention relates to voltage regulators. More particularly, the present invention relates to voltage regulator that employs a switching circuit having a pulse width modulator controlled by a high speed buffer circuit employed in a master-slave topology for fast response to rapidly changing load current.
2. The Prior Art
As the number of transistors employed in an integrated circuit increases, particularly for example in a microprocessor, the requirements for supplying power to the integrated circuit have become more demanding. It is presently contemplated that as the Vcc in a microprocessor drops to approximately 1 to 1.5 volts, the current required by the microprocessor will be in a range of about 35 to about 50 amps. Accordingly, the power dissipation in the microprocessor will be at least 50 watts.
To conserve power in a multitude of applications, such as a notebook computer, the microprocessor will switch into a sleep mode, as is presently understood by those of ordinary skill in the art. When the microprocessor is switched from sleep mode to a waking mode, current must be provided very quickly. For a microprocessor operating a 1 GHz it is anticipated that 50 amps of current must be provided at a slew rate of approximately 1 amp/nanosecond at the power pins of the microprocessor. A further requirement is that the supply voltage of the microprocessor should be kept within a tolerance band of that does not exceed approximately 2-3%. Traditional linear and conventional switched regulators well known to those of ordinary skill in the art are respectively too inefficient in meeting these requirements or too slow to meet these requirements.
In a typical linear power supply or voltage regulator circuit, a linear control element, such as a pass transistor, in series with an unregulated DC is used, with feedback, to maintain a constant output voltage. The output voltage is always lower in voltage than the unregulated input voltage, and some power is dissipated in the control element. Though the linear power supply has a fast response time, it is not very efficient. As such, it is it is not a realistic approach to proving power in many integrated circuit applications.
In a switching converter, a transistor is typically operated as a saturated switch that periodically applies the full unregulated voltage across an inductor for short intervals. The current in the inductor builds up during each pulse, storing 1/2 LI.sup.2 of energy in its magnetic field. The stored energy is transferred to a filter capacitor at the output that also smooths the output by carrying the output load between the charging pulses. In order to accommodate rapid and transient load changes, and to filter the switch frequency from the output, the output capacitor preferably has a large value with a very low equivalent series resistance (ESR). With feedback, the output of the converter is compared with an input preset reference to control the switching frequency or pulse width of the signal applied to the transistor operated as a switch. Since the control element is either off or on, the power dissipation in the regulator is minimized. Accordingly, switching regulators are very efficient, even when there is a large voltage drop from the input to the output. However, there is limitation on how quickly a switching converter can provide current to readily changing load condition.
In FIG. 1, a known DC-DC converter 10, referred to by those of ordinary skill in the art as a step-down or "buck" topology, is illustrated. In converter 10, the switching speed of a MOSFET transistor 12 is controlled by the output a comparator 14 fed through a driver 16 and coupled to the gate of MOSFET transistor 12. The comparator 14 has an inverting input connected to a signal that in this example oscillates between 0 and 2 volts, and a non-inverting input connected to a feedback loop to form a pulse width modulator (PWM). The drain of MOSFET transistor 12 is connected to Vin, and the source of MOSFET transistor 12 is connected a first terminal of inductor 18 and the anode of Schotky diode 20. In this example the inductor has a value of 10 uH. The second terminal of inductor 18 is connected to a first plate of load capacitor 20. A second plate of load capacitor 20 is connected to the cathode of Schotky diode 18 and to a ground reference potential to complete a loop for current circulation. The common connection of the second terminal of inductor 18 and the first plate of capacitor 20 forms the output node Vout of the switching converter 10.
The output node Vout is also coupled to a first end of first impedance block 24 in a feedback loop. A second end of impedance block 24 is coupled to the inverting input of error amplifier 26. A second impedance block 28 provides feedback to error amplifier 26 in a manner well understood by those of ordinary skill in the art. The non-inverting input of error amplifier 26 is connected to a reference potential Vref. The output of error amplifier 24 is connected to the inverting input of comparator 14 to complete the feed back loop to the MOSFET transistor 12.
In the switching converter 10, a higher input voltage at Vin is converted to a lower input voltage at Vout. When the MOSFET transistor 12 is turned on by the output of comparator 14, the voltage Vin-Vout is applied across the inductor 18, causing a linearly increasing current to flow through the inductor 18. When the MOSFET transistor 12 is turned off by the output of comparator 14, inductor current continues to flow in the same direction with the Schotky diode 22 conducting to complete the circuit. Since the voltage across the inductor 18 is now the sum of Vout and the nominal voltage of the Schotky diode 22, the inductor current will decrease linearly. The load capacitor 20 operates to minimize current and voltage ripple at the output of the switching converter 10. It will be appreciated that as the size of the capacitor 20 increases, the amount of ripple decreases, however, the response time of the converter 10 to changes in the load also increases.
As the load at Vout changes, the feedback loop including the error amplifier 26 forms a control circuit to ensure that Vout remains at a desired value with a high degree of precision. In the feedback loop, Vout is compared to Vref. The difference between Vref and Vout determines the width of the pulse from comparator 14 driving the MOSFET transistor 12 to control the amount of energy delivered to a load in a manner well understood by those of ordinary skill in the art.
A schematic model 30 of capacitor 20 including the ESR 32 and the ESL 34 is illustrated in FIG. 2. The minimum impedance of capacitor 20 is achieved for the frequency, F.sub.o, at which the ESR is minimized. This frequency is found according to the following well known relation. ##EQU1## For a well rated capacitor 20, this will provide a frequency of approximately 1 MHz. It will be appreciated by those of ordinary skill in the art that the impedance of the capacitor 20 should be made as small as possible so that the rate of current being supplied to the load will be adequate before the current in the inductor 18 can be built up. With a 10 uH inductor having a voltage drop of 5 volts to 2 volts across its terminals, current will be provided at a rate of about only 3 mA/nS. Accordingly, other solutions for providing current to the load at an acceptable rate have been sought.
In one approach disclosed in European patent application EP 0 699 986 A2 to Danstrom, a switching regulator is disposed in series with a linear regulator. The switching regulator forms a front-end to control the input voltage of the linear regulator to prevent power loss in the linear regulator. This approach is not that efficient because current continuously flows through the linear regulator.
In another approach disclosed in U.S. Pat. No. 5,258,701 to Pizzi et al., a switching regulator is disposed in parallel with a linear regulator. Both the switching regulator and the linear regulator are independently controlled. The reference voltage of the switching regulator is set at a higher voltage level than that of the linear regulator. Unless the transient load results in the output voltage falling below that of the reference voltage of the linear regulator, the linear regulator is in a shut-off mode.
In a further approach disclosed in the data sheet for part nos. HIP6200 and HIP6201 manufactured by Harris Semiconductor published February 1998, an independently controlled buffer circuit is disposed in parallel with a switching regulator. There is a preset tolerance band for the output voltage. When the output voltage goes out of this tolerance band, the buffer circuit responds with a preset current source or current sink. The manner of control is provided through hysterisis by sensing the output voltage.
In both the Pizzi et al. and Harris Semiconductor approaches, there is lack of a control mechanism to force the switch regulator current to equal the load current. This requires that the switching regulator have a tight voltage band tolerance. This can be a problem because it requires matching two independently set reference voltages. Further, in microprocessor application, tight voltage band tolerance may not be feasible because for some static regulation errors bigger transient voltage spikes are permitted.
Accordingly, it is an object of the present invention to provide a voltage regulator having a switching regulator in combination with a linear regulator that does not exhibit the drawbacks found in prior art approaches.